use moparse_lib::VerilogParser;

fn main() {
    let parser = VerilogParser::new();
    
    // Test the problematic concatenation
    let test_expr = "{CLK_REF_PCIE3_PHY3_P,CLK_REF_PCIE3_PHY2_P,CLK_REF_PCIE3_PHY1_P,CLK_REF_PCIE3_PHY0_P}";
    println!("Testing expression: {}", test_expr);
    
    let signals = parser.extract_signal_names(test_expr);
    println!("Extracted signals: {:?}", signals);
    
    // Test the parse_replication function
    if let Some((count, expr)) = parser.parse_replication(test_expr) {
        println!("Replication detected: {} times '{}'", count, expr);
    } else {
        println!("No replication detected");
    }
    
    // Test split_concatenation
    if test_expr.starts_with('{') && test_expr.ends_with('}') {
        let inner = &test_expr[1..test_expr.len()-1];
        println!("Inner content: '{}'", inner);
        let parts = parser.split_concatenation(inner);
        println!("Split parts: {:?}", parts);
    }
}